1. Field of the Invention
The present invention relates to a thin film transistor used in a display panel such as a liquid crystal display panel, and a process for fabricating the same. In this specification, the thin film transistor will be referred to as "TFT".
2. Description of the Prior Art
FIGS. 7a and 7b, and FIGS. 8a and 8b show a known process for fabricating a TFT which use amorphous silicon used for a liquid crystal display panel. FIGS. 7b and 8b are respectively cross-sectional views of FIGS. 7a and 8a, taken along the line B--B. The TFT is fabricated as follows:
Tantalum is deposited on the whole surface of a glass substrate 1 by sputtering. A gate bus line 2 is formed by patterning the Ta layer. Anodic oxidization is performed on the upper surface of the gate bus line 2 to form an anodic oxide layer 3. Then, a gate insulating layer 4 of SiN.sub.x, a semiconductor layer 15 of intrinsic semiconductor amorphous silicon (hereinafter referred to as "a-Si(i)") which later becomes a channel layer 5 for the TFT, and a second SiN.sub.x layer which later becomes a protective back layer 6 are successively layered by a CVD method. In addition, a photoresist mask 7 is formed by patterning a first photoresist formed on the second SiN.sub.x layer. Then, a semiconductor layer 15 is etched using the protective back layer 6 as an etching mask to form the channel layer 5 (FIG. 8a and 8b).
Finally, the whole surface of the substrate 1 including the protective back layer 6 is covered with an insulating layer such as SiN.sub.x, and the usual procedure is pursued to form a TFT.
The TFT fabricated by the above-mentioned process has the following disadvantages:
When the channel layer 5 is to be patterned, the side face thereof is exposed between the gate insulating layer 4 and the protective back layer 6, thereby allowing foreign materials to be stuck to the exposed side face. The failure to remove such foreign materials is likely to cause problems. In addition, when the channel layer 5 is formed by etching using the protective back layer 6 as the etching mask in a liquid, the channel layer 5 is often excessively etched, thereby causing the protective back layer 6 to extend over the channel layer 5 like eaves as shown in FIG. 8b. In this case, the side face of the channel layer 5 is exposed under the eaves between the gate insulating layer 4 and the protective back layer 6, so that it is more difficult to remove the foreign materials adhered to the exposed side face.
In order to avoid forming the detrimental eaves, one way is to remove the protective back layer 6 after the channel layer 5 is formed, and then to pattern the insulating layer. However, because the channel layer 5 is only a few hundreds angstroms thin that the removal of the protective back layer 6 and the subsequent cleaning are likely to unfavorably affect the channel layer 5. The adherence of foreign matters to the exposed channel layer 5 per se is a problem.
If the TFT is fabricated with the foreign materials adhering to the channel layer 5, the foreign materials are likely to react with the a-Si(i) component of the channel layer 5, and cause various problems such as an electrical short circuit between the source electrode and the drain electrode of the TFT, a low yield of the TFT production such as reduced conductivity, and inconsistent electrical characteristics of the TFT.